FN6659 datasheet(29/32 Pages) RENESAS

29 / 32 page

ISL12022

FN6659 Rev.3.01

Page 29 of 32

Oct 24, 2019

Temperature Compensation Operation

The ISL12022 temperature compensation feature needs to be

enabled by the user. This must be done in a specific order as

follows.

1. Read register 0Dh, the BETA register. This register contains the

5-bit BETA trimmed value which is automatically loaded on initial

power-up. Mask off the 5LSB’s of the value just read.

2. Bit 7 of the BETA register is the master enable control for

temperature sense operation. Set this to “1” to allow

continuous temperature frequency correction. Frequency

correction will then happen every 60s with VDD applied.

3. Bits 5 and 6 of the BETA register control temperature

compensation in battery-backup mode (see Table 15). Set the

values for the operation desired.

4. Write back to register 0Dh making sure not to change the 5

LSB values, and include the desired compensation control bits.

Note that every time the BETA register is written with the TSE

bit = 1, a temperature compensation cycle is instigated and a

new correction value will be loaded into the FATR/FDTR registers

(if the temperature changed since the last conversion).

Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA

registers, should not be changed. If they must be written be sure

to write the same values that are recalled from initial power-up.

The ITR0 register may be written if the user wishes to re-calibrate

the oscillator frequency at room temperature for aging or board

mounting. The original recalled value can be re-written if desired

after testing.

For further information on the operation of the ISL12022 and

temperature compensated RTC’s, see Intersil Application Note

AN1389, “Using Intersil’s High Accuracy Real Time Clock

Module”.

Daylight Savings Time (DST) Example

DST involves setting the forward and back times and allowing the

RTC device to automatically advance the time or set the time back.

This can be done for current year, and future years. Many regions

have DST rules that use standard months, weeks and time of the

day which permit a pre-programmed, permanent setting.

Table 27 shows the example setup for the ISL12022.

The Enable bit (DSTE) is in the Month forward register, so the BCD

value for that register is altered with the additional bit. The Week

and Day values along with Week/Day vs Date select bit is in the

Week/Day register, so that value is also not straight BCD. Hour

and Month are normal BCD, but the Hour doesn’t use the MIL bit

since Military time PM values are already discretely different

from AM/PM time PM values. The DST reverse setting utilizes the

option to select the last week of the month for October, which

could have 4 or 5 weeks but needs to have the time change on

the last Sunday.

Note that the DSTADJ bit in the status register monitors whether

the DST forward adjustment has happened. When it is “1”, DST

forward has taken place. When it is “0”, then either DST reverse

has happened, or it has been reset either by initial power-up or if

the DSTE bit has been set to “0”.

TABLE 27. DST EXAMPLE

VARIABLE

VALUE

Month Forward and DST Enable

April

15h

84h

Week and Day Forward and select

Day/Week, not Date

1st Week and

Sunday

16h

48h

Date Forward

not used

17h

00h

Hour Forward

2am

18h

02h

Month Reverse

October

19h

10h

Week and Day Reverse and select

Day/Week, not Date

Last Week and

Sunday

1Ah

78h

Date Reverse

not used

1Bh

00h

Hour Reverse

2am

1Ch

02h

FN6659 Datasheet(PDF) 29 Page - Renesas Technology Corp

FN6659 Datasheet(HTML) 29 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL