ISL12022

FN6659 Rev.3.01

Page 7 of 32

Oct 24, 2019

tR

SDA and SCL Rise Time

From 30% to 70% of VDD.

20 + 0.1 x Cb

300

ns

12

tF

SDA and SCL Fall Time

From 70% to 30% of VDD.

20 + 0.1 x Cb

300

ns

12

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

10

400

pF

12

RPU

SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by tR

and tF.

For Cb = 400pF, max is about

2kΩ~2.5kΩ.

For Cb = 40pF, max is about

15kΩ~20kΩ

1

kΩ

12

NOTES:

6. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT <1.8V.

7. IRQ/FOUT inactive.

8. VDD > VBAT +VBATHYS.

9. Specified at +25°C.

10. To ensure proper timekeeping, the VDD SR- specification must be followed.

11. Limits should be considered typical and are not production tested.

12. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.

13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

14. Specifications are typical and require using a recommended crystal (see “Application Section” on page 26).

15. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested.

16. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.

I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified.

Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 13)

TYP

(Note 9)

MAX

(Note 13)UNIT

NOTES