FN6659 datasheet(20/32 Pages) RENESAS

20 / 32 page

ISL12022

FN6659 Rev.3.01

Page 20 of 32

Oct 24, 2019

If the application has a stable temperature environment that

doesn’t change quickly, the 10 minute option will work well and

the backup battery lifetime impact is minimized. If quick

temperature variations are expected (multiple cycles of more

than 10° within an hour), then the 1 minute option should be

considered and the slightly higher battery current figured into

overall battery life.

GAIN FACTOR OF AT BIT (BETA<4:0>)

Beta is specified to take care of the Cm variations of the crystal.

Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF,

the actual AT steps may reduce from 1ppm/step to

approximately 0.80ppm/step. Beta is then used to adjust for this

variation and restore the step size to 1ppm/step.

BETA values are limited in the range from 01000 to 11111 as

shown in Table 16

. To use Table 16, the device is tested at two

AT settings as shown in Equation 3:

where:

AT(max) = FOUT in ppm (at AT = 00H) and

AT(min) = FOUT in ppm (at AT = 3FH).

The BETA VALUES result is indexed in the right hand column and

the resulting Beta factor (for the register) is in the same row in

the left column.

The value for BETA should only be changed while the TSE

(Temperature Sense Enable) bit is “0”. The procedure for writing

the BETA register involves two steps. First, write the new value of

BETA with TSE = 0. Then write the same value of BETA with

TSE = 1. This will insure the next temperature sense cycle will use

the new BETA value.

Final Analog Trimming Register (FATR)

This register shows the final setting of AT after temperature

correction. It is read-only; the user cannot overwrite a value to this

temperature compensation function. See Table 17.

Final Digital Trimming Register (FDTR)

This Register shows the final setting of DT after temperature

correction. It is read-only; the user cannot overwrite a value to

this register. The value is accessible as a means of monitoring

the temperature compensation function. The corresponding

clock adjustment values are shown in Table 19. The DT setting

has both positive and negative settings to adjust for any offset in

the crystal.

TABLE 16. BETA VALUES

BETA<4:0>

AT STEP ADJUSTMENT

01000

0.5000

00111

0.5625

00110

0.6250

00101

0.6875

00100

0.7500

00011

0.8125

00010

0.8750

00001

0.9375

00000

1.0000

10000

1.0625

10001

1.1250

10010

1.1875

10011

1.2500

10100

1.3125

10101

1.3750

10110

1.4375

BETAVALUES

AT max

 AT min



–

/63

(EQ. 3)

10111

1.5000

11000

1.5625

11001

1.6250

11010

1.6875

11011

1.7500

11100

1.8125

11101

1.8750

11110

1.9375

11111

2.0000

TABLE 17. FINAL ANALOG TRIMMING REGISTER

ADDR

0Eh

FATR5 FATR4 FATR3 FATR2 FATR1 FATR0

TABLE 18. FINAL DIGITAL TRIMMING REGISTER

ADDR

765

0Fh

FDTR4 FDTR3 FDTR2 FDTR1 FDTR0

TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL

TRIMMING REGISTER

FDTR<4:0>

DECIMAL

ppm ADJUSTMENT

00000

00001

30.5

00010

00011

91.5

00100

122

00101

152.5

00110

183

00111

213.5

01000

244

01001

274.5

TABLE 16. BETA VALUES (Continued)

BETA<4:0>

AT STEP ADJUSTMENT

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