FN6659 datasheet(25/32 Pages) RENESAS

25 / 32 page

ISL12022

FN6659 Rev.3.01

Page 25 of 32

Oct 24, 2019

User Registers (Accessed by

Using Slave Address 1010111x)

Addresses [00h to 7Fh]

These registers are 128 bytes of battery-backed user SRAM.

I2C Serial Interface

The ISL12022 supports a bi-directional bus oriented protocol. The

protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The device

controlling the transfer is the master and the device being controlled

is the slave. The master always initiates data transfers and provides

the clock for both transmit and receive operations. Therefore, the

ISL12022 operates as a slave device in all applications.

All communication over the I2C interface is conducted by sending

the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL LOW

periods. SDA state changes during SCL HIGH are reserved for

indicating START and STOP conditions (see Figure 15). On power-

up of the ISL12022, the SDA pin is in the input mode.

All I2C interface operations must begin with a START condition,

which is a HIGH to LOW transition of SDA while SCL is HIGH. The

ISL12022 continuously monitors the SDA and SCL lines for the

START condition and does not respond to any command until this

condition is met (see Figure 15). A START condition is ignored

during the power-up sequence.

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL is

HIGH (see Figure 15). A STOP condition at the end of a read

operation or at the end of a write operation to memory only

places the device in its standby mode.

An acknowledge (ACK) is a software convention used to indicate a

successful data transfer. The transmitting device, either master or

slave, releases the SDA bus after transmitting eight bits. During

the ninth clock cycle, the receiver pulls the SDA line LOW to

acknowledge the reception of the 8 bits of data (see Figure 16).

FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)

SDA

SCL

START

DATA

STOP

STABLE

CHANGE

DATA

STABLE

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

START

ACK

SCL FROM

MASTER

HIGH IMPEDANCE

IDENTIFICATION

BYTE

DATA

BYTE

SIGNALS FROM

THE MASTER

SIGNALS FROM

THE ISL12022

WRITE

SIGNAL AT SDA

00 00

11 1

ADDRESS

BYTE

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