FN6659 datasheet(15/32 Pages) RENESAS

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ISL12022

FN6659 Rev.3.01

Page 15 of 32

Oct 24, 2019

Real Time Clock Registers

Addresses [00h to 06h]

RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)

These registers depict BCD representations of the time. As such,

SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour)

can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31,

MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the

Week) is 0 to 6.

The DW register provides a Day of the Week status and uses three

bits DW2 to DW0 to represent the seven days of the week. The

counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-…

The assignment of a numerical value to a specific day of the

week is arbitrary and may be decided by the system software

designer. The default value is defined as “0”.

24 HOUR TIME

If the MIL bit of the HR register is “1”, the RTC uses a

24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour

format and HR21 bit functions as an AM/PM indicator with a “1”

representing PM. The clock defaults to 12-hour format time with

HR21 = “0”.

LEAP YEARS

Leap years add the day February 29 and are defined as those years

that are divisible by 4. Years divisible by 100 are not leap years,

unless they are also divisible by 400. This means that the year 2000

is a leap year and the year 2100 is not. The ISL12022 does not

correct for the leap year in the year 2100.

Control and Status Registers

(CSR)

Addresses [07h to 0Fh]

The Control and Status Registers consist of the Status Register,

Interrupt and Alarm Register, Analog Trimming and Digital

Trimming Registers.

Status Register (SR)

The Status Register is located in the memory map at address

07h. This is a volatile register that provides either control or

status of RTC failure (RTCF), Battery Level Monitor (LBAT85,

LBAT75), alarm trigger, Daylight Savings Time, crystal oscillator

enable and temperature conversion in progress bit.

BUSY BIT (BUSY)

Busy Bit indicates temperature sensing is in progress. In this

mode, Alpha, Beta and ITRO registers are disabled and cannot be

accessed.

OSCILLATOR FAIL BIT (OSCF)

Oscillator Fail Bit indicates that the oscillator has failed. The

oscillator frequency is either zero or very far from the desired

32.768kHz due to failure, PC board contamination or mechanical

issues.

DAYLIGHT SAVINGS TIME CHANGE BIT (DSTADJ)

DSTADJ is the Daylight Savings Time Adjusted Bit. It indicates the

daylight saving time forward adjustment has happened. If a DST

Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit

will stay high after the DSTFD event happens, and will be reset to

“0” when the DST Reverse event happens. It is read-only and

cannot be written. Setting time during a DST forward period will

not set this bit to “1”.

The DSTE bit must be enabled when the RTC time is more than

one hour before the DST Forward or DST Reverse event time

setting, or the DST event correction will not happen.

DSTADJ is reset to “0” upon power-up. It will reset to ”0” when the

DSTE bit in Register 15h is set to “0” (DST disabled), but no time

adjustment will happen.

ALARM BIT (ALM)

This bit announces if the alarm matches the real time clock. If

there is a match, the respective bit is set to “1”. This bit can be

manually reset to “0” by the user or automatically reset by

enabling the auto-reset bit (see ARST bit). A write to this bit in the

SR can only set it to “0”, not “1”. An alarm bit that is set by an

alarm occurring during an SR read operation will remain set after

the read operation is complete.

LOW VDD INDICATOR BIT (LVDD)

This bit indicates when VDD has dropped below the pre-selected

trip level (Brownout Mode). The trip points for the brownout levels

are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in

PWR_ VDD registers. The LVDD detection is only enabled in VDD

mode and the detection happens in real time. The LVDD bit is set

whenever the VDD has dropped below the pre-selected trip level,

and self clears whenever the VDD is above the pre-selected trip

level.

LOW BATTERY INDICATOR 85% BIT (LBAT85)

In Normal Mode (VDD), this bit indicates when the battery level

has dropped below the pre-selected trip levels. The trip points are

selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the

PWR_VBAT registers. The LBAT85 detection happens

automatically once every minute when seconds register reaches

59. The detection can also be manually triggered by setting the

TSE bit in BETA register to “1”. The LBAT85 bit is set when the

VBAT has dropped below the pre-selected trip level, and will self

clear when the VBAT is above the pre-selected trip level at the

next detection cycle either by manual or automatic trigger.

In Battery Mode (VBAT), this bit indicates the device has entered

into battery mode by polling once every 10 minutes. The LBAT85

detection happens automatically once when the minute register

reaches x9h or x0h minutes.

TABLE 2. STATUS REGISTER (SR)

ADDR

07h

BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF

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