FN6659 datasheet(17/32 Pages) RENESAS

17 / 32 page

ISL12022

FN6659 Rev.3.01

Page 17 of 32

Oct 24, 2019

POWER SUPPLY CONTROL REGISTER (PWR_VDD)

Clear Time Stamp Bit (CLRTS)

This bit clears Time Stamp VDD to Battery (TSV2B) and Time

Stamp Battery to VDD Registers (TSB2V). The default setting is 0

(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).

VDD Brownout Trip Voltage BITS (VDDTrip<2:0)

These bits set the 6 trip levels for the VDD alarm, indicating that

VDD has dropped below a preset level. In this event, the LVDD bit

in the Status Register is set to “1”. See Table 6.

Battery Voltage Trip Voltage Register

(PWR_VBAT)

This register controls the trip points for the two VBAT alarms, with

levels set to approximately 85% and 75% of the nominal battery

level.

RESEAL BIT (RESEALB)

This is the Reseal bit for actively disconnecting VBAT pin from the

internal circuitry. Setting this bit allows the device to disconnect the

battery and eliminate standby current drain while the device is

unused. Once VDD is powered up, this bit is reset and the VBAT pin is

then connected to the internal circuitry.

The application for this bit involves placing the chip on a board

with a battery and testing the board. Once the board is tested

and ready to ship, it is desirable to disconnect the battery to keep

it fresh until the board or unit is placed into final use. Setting

RESEALB = “1” initiates the battery disconnect, and after VDD

power is cycled down and up again, the RESEAL bit is cleared

to “0”.

BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)

Three bits select the first alarm (85% of Nominal VBAT) level for the

battery voltage monitor. There are total of 7 levels that could be

selected for the first alarm. Any of the of levels could be selected as

the first alarm with no reference as to nominal Battery voltage level.

See Table 8.

BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)

Three bits select the second alarm (75% of Nominal VBAT) level for

the battery voltage monitor. There are total of 7 levels that could be

selected for the second alarm. Any of the of levels could be selected

as the second alarm with no reference as to nominal Battery voltage

level. See Table 9.

Initial AT and DT Setting Register (ITRO)

These bits are used to trim the initial error (at room temperature)

of the crystal. Both Digital Trimming (DT) and Analog Trimming

(AT) methods are available. The digital trimming uses clock pulse

skipping and insertion for frequency adjustment. Analog

000

001

010

1/2

011

1/4

100

1/8

101

1/16

110

1/32

ADDR

09h

CLRTS

VDDTrip2 VDDTrip1 VDDTrip0

TABLE 6. VDD TRIP LEVELS

VDDTrip2

VDDTrip1

VDDTrip0

TRIP VOLTAGE

(V)

2.295

2.550

2.805

3.060

4.250

4.675

TABLE 7.

ADDR 7

4321

0Ah

D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0

TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN (Continued)

FREQUENCY,

FOUT

UNITS

FO3

FO2

FO1

FO0

TABLE 8. VB85T ALARM LEVEL

VB85Tp2

VB85Tp1

VB85Tp0

BATTERY ALARM

TRIP LEVEL

(V)

2.125

2.295

2.550

2.805

3.060

4.250

4.675

TABLE 9. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)

VB75Tp2

VB75Tp1

VB75Tp0

BATTERY ALARM

TRIP LEVEL

(V)

1.875

2.025

2.250

2.475

2.700

3.750

4.125

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