FN6659 datasheet(21/32 Pages) RENESAS

21 / 32 page

ISL12022

FN6659 Rev.3.01

Page 21 of 32

Oct 24, 2019

ALARM Registers (10h to 15h)

The alarm register bytes are set up identical to the RTC register

bytes, except that the MSB of each byte functions as an enable

bit (enable = “1”). These enable bits specify which alarm

registers (seconds, minutes, etc.) are used to make the

comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the alarm

registers and the RTC registers. As the RTC advances, the alarm

will be triggered once a match occurs between the alarm registers

and the RTC registers. Any one alarm register, multiple registers, or

all registers can be enabled for a match.

There are two alarm operation modes: Single Event and periodic

Interrupt Mode:

• Single Event Mode is enabled by setting the bit 7 on any of the

Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and

disabling the frequency output. This mode permits a one-time

match between the Alarm registers and the RTC registers.

Once this match occurs, the ALM bit is set to “1” and the

IRQ/FOUT output will be pulled low and will remain low until

the ALM bit is reset. This can be done manually or by using the

auto-reset feature.

• Interrupt Mode is enabled by setting the bit 7 on any of the

Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1”, and

disabling the frequency output. The IRQ/FOUT output will now

be pulsed each time an alarm occurs. This means that once

the interrupt mode alarm is set, it will continue to alarm for

each occurring match of the alarm and present time. This

mode is convenient for hourly or daily hardware interrupts in

microcontroller applications such as security cameras or utility

meter reading.

To clear a single event alarm, the ALM bit in the status register

must be set to “0” with a write. Note that if the ARST bit is set

to 1 (address 08h, bit 7), the ALM bit will automatically be

cleared when the status register is read.

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1

• Alarm set with single interrupt (IM = ”0”)

• A single alarm will occur on January 1 at 11:30 a.m.

• Set Alarm registers as follows:

After these registers are set, an alarm will be generated when the

RTC advances to exactly 11:30 a.m. on January 1 (after seconds

changes from 59 to 00) by setting the ALM bit in the status register

to “1” and also bringing the IRQ/FOUT output low.

Example 2

• Pulsed interrupt once per minute (IM = ”1”)

• Interrupts at one minute intervals when the seconds register is

at 30s.

• Set Alarm registers as follows:

Once the registers are set, the following waveform will be seen at

IRQ/FOUT:

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

01010

305

10000

10001

-1

-30.5

10010

-2

-61

10011

-3

-91.5

10100

-4

-122

10101

-5

-152.5

10110

-6

-183

10111

-7

-213.5

11000

-8

-244

11001

-9

-274.5

11010

-10

-305

TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL

TRIMMING REGISTER (Continued)

FDTR<4:0>

DECIMAL

ppm ADJUSTMENT

ALARM

BIT

DESCRIPTION

76543 210

HEX

SCA0

000000 00

00h Seconds disabled

MNA0

101100 00

B0h Minutes set to 30,

enabled

HRA0

100100 01

91h Hours set to 11,

enabled

DTA0

100000 01

81h Date set to 1,

enabled

MOA0

100000 01

81h Month set to 1,

enabled

DWA0

000000 00

00h Day of week

disabled

ALARM

BIT

DESCRIPTION

7 654 3210 HEX

SCA0

1011 0000 B0h Seconds set to 30,

enabled

MNA0

0000 0000 00h Minutes disabled

HRA0

0000 0000 00h Hours disabled

DTA0

0000 0000 00h Date disabled

MOA0

0000 0000 00h Month disabled

DWA0

0000 0000 00h Day of week disabled

60s

RTC AND ALARM REGISTERS ARE BOTH “30s”

FIGURE 14. IRQ/FOUT WAVEFORM

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