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LT3040 Datasheet(PDF) 5 Page - Analog Devices

Part # LT3040
Description  20V, 200mA, Ultralow Noise, Ultrahigh PSRR Precision DAC/Reference Buffer
PDF  30 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LT3040 Datasheet(HTML) 5 Page - Analog Devices

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LT3040
5
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The EN/UV pin threshold must be met to ensure device operation.
Note 3: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of supply voltage and output current, especially due to
the internal current limit foldback that starts to decrease current limit at
V+ – VOUT > 12V. If operating at maximum output current, limit the supply
voltage range. If operating at the maximum supply voltage, limit the output
current range.
Note 4: VFB tied directly to OUT.
Note 5: Dropout voltage is the minimum supply-to-output differential
voltage needed to maintain regulation at a specified output current. The
dropout voltage is measured when output is 1% out of regulation. This
definition results in higher dropout voltage compared to hard dropout—
which is measured when V+ = VOUT(NOMINAL). For lower output voltages,
below 1.5V, dropout voltage is limited by the minimum supply voltage
specification. Analog Devices is unable to guarantee maximum dropout
voltage specifications for DFN package at high currents due to production
test limitations with Kelvin sensing the package pins. Please consult the
Typical Performance Characteristics for curves of dropout voltage as a
function of output load current and temperature measured in a typical
application circuit.
Note 6: GND pin current is tested with V+ = VOUT(NOMINAL) and a current
source load. Therefore, the device is tested while operating in dropout.
This is the worst-case GND pin current. GND pin current decreases at
higher supply voltages. Note that GND pin current does not include ILIM
pin current but quiescent current does include it.
Note 7: VIN and VFB pins are clamped using diodes and two 25Ω series
resistors. For less than 5ms transients, this clamp circuitry can carry more
than the rated current. See Typical Performance Characteristics and refer
to Applications Information for more information.
Note 8: Adding a capacitor at the VIN pin decreases output voltage noise.
Adding this capacitor bypasses the reference voltage source’s or the DAC’s
noise. The output noise then equals the error amplifier noise. Use of a VIN
pin bypass capacitor also increases start-up time.
Note 9: The LT3040 is tested and specified under pulsed load conditions
such that TJ ≈ TA. The LT3040E is 100% tested at 25°C and performance
is guaranteed from 0°C to 125°C. Specifications over the –40°C to 125°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LT3040I is guaranteed
over the full –40°C to 125°C operating temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
Note 10: Parasitic diodes exist internally between the ILIM, VIN, FS, FAULT,
VFB and OUT pins and the GND pin. Do not drive these pins more than
0.3V below the GND pin during a fault condition. These pins must remain
at a voltage more positive than GND during normal operation.
Note 11: The current limit programming scale factor is specified while the
internal backup current limit is not active. Note that the internal current
limit has foldback protection for V+ – VOUT differentials greater than 12V
Note 12: The internal back-up current limit circuitry incorporates fold-back
protection that decreases current limit for V+ – VOUT > 12V. Some level of
output current is provided at all V+ – VOUT differential voltages. Consult the
Typical Performance Characteristics graph for current limit vs V+ – VOUT.
Note 13: For an output voltage less then 1V, the LT3040 requires a 10µA
minimum load current for stability.
Note 14: Maximum OUT-to-VFB differential is guaranteed by design.
Note 15: The bias current cancellation circuit used to cancel any IR drop
across external resistors does not operate for VIN pin voltages below
100mV due to circuit limitations. As a result, the bias current increases
exponentially below this voltage. See Typical Performance Characteristics
Note 16: The Offset Voltage specification does not include the effects of
line and load regulation.
Note 17: Deviations in output voltage from the reference setpoint are
cumulative; errors in output regulation due to offset, line and load
regulation add up.
Note 18: Hysteresis in the offset voltage is created by package stress
that differs depending on whether the IC was previously at a higher
or lower temperature. Offset voltage is always measured at 25°C, but
the IC is cycled to the hot or cold temperature limit before successive
measurements. Hysteresis measures the maximum output change for
the averages of three hot or cold temperature cycles. For instruments
that are stored at well controlled temperatures (within 20 to 30 degrees
of operational temperature), it’s usually not a dominant error source.
Typical hysteresis is the worst-case of 25°C to cold to 25°C to hot to 25°C,
preconditioned by one thermal cycle.
Note 19: To achieve rail-to-rail output operation, LT3040 uses either a PNP
or a NPN input differential pair. There is a transition from the PNP to NPN
differential pair at around the 0.9V with a typical hysteresis of about 35mV.
See Applications Section for more information.
Note 20: Long-term stability typically has a logarithmic characteristic.
Changes after 1000 hours tend to be much smaller than before that time.
Total drift in the second thousand hours is normally less than one-third
that of the first thousand hours with a continuing trend toward reduced
drift with time. Long-term stability is also affected by differential stresses
between the IC and the board material created during board assembly.
Note 21: Dropout voltage measurements are done by forcing a voltage at
the VIN pin.



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