LT3040 datasheet(16/30 Pages) AD

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LT3040

Rev. 0

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The LT3040 is a high performance low dropout voltage

buffer featuring ADI’s ultralow noise (4nV/√Hz at 10kHz)

and ultrahigh PSRR (73dB at 1MHz) architecture for pow-

ering noise sensitive applications. Designed as a high-

performance rail-to-rail voltage buffer, the LT3040 can be

easily paralleled to further reduce noise, increase output

current and spread heat on the PCB. The device addition-

ally features programmable current limit, fast start-up

capability and fault indicator flag.

The LT3040 is easy to use and incorporates all of the pro-

tection features expected in a high-performance voltage

buffer. Included are short-circuit protection, safe operat-

ing area protection, reverse supply voltage protection,

reverse current protection and thermal shutdown with

hysteresis.

Output Voltage

The LT3040’s rail-to-rail error amplifier allows for a wide

output voltage range from 0V to V+ minus dropout—up

to 15V. A PNP-based input pair is active for 0V to ~0.9V

output and an NPN-based input pair is active for output

voltages greater than ~0.9V, with an abrupt transition

between the two input pairs at ~0.9V output with approxi-

mately 35mV of hysteresis. The NPN-based input pair is

designed to offer the best overall performance. Refer to

the Electrical Characteristics table for details on offset

voltage, VIN offset pin current, output noise and PSRR

variation with the error amp input pair.

The PNP and the NPN input pairs are trimmed separately

for offset voltage. As a result, the PNP and the NPN offsets

could end up significantly different from each other within

the offset limits specified in the EC table. The offset volt-

age behavior in the transition region for a typical part is

as shown in Figure 1. The range of variation in the offset

voltage is shown in Figure 2.

The LT3040 always operates in unity gain configuration.

This allows the LT3040 to have loop gain, frequency

response and bandwidth independent of the output volt-

age. As a result, noise, PSRR and transient performance

do not change with output voltage. Moreover, since none

APPLICATIONS INFORMATION

of the error amp gain is needed to amplify the VIN pin

voltage to a higher output voltage, output load regulation

is more tightly specified in the hundreds of microvolts

range and not as a fixed percentage of the output voltage.

If an application uses the LT3040 with a filter resistor from

FS to VIN or a current limit resistor into VIN, any leakage

paths to or from the VIN pin create errors in the output

voltage. If necessary, use high quality insulation (e.g.,

Teflon, Kel-F); moreover, cleaning of all insulating surfaces

to remove fluxes and other residues may be required.

High humidity environments may require a surface coat-

ing at the VIN pin to provide a moisture barrier.

Figure 1.

VIN RISING

VIN FALLING

VIN (V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0

–100

–80

–60

–40

–20

100

3040 F01

PNP to NPN Diff Pair Transition

Figure 2.

TJ = 25°C

ILOAD=1mA

VOS[VIN = 0.95V]–VOS[VIN = 0.85V] (µV)

–150 –100

–50

100

150

100

3040 F02

PNP to NPN VOS Distribution

LT3040 Datasheet(PDF) 16 Page - Analog Devices

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