LTM2886 datasheet(18/38 Pages) AD

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LTM2886

Rev C

For more information www.analog.com/LTM2886

APPLICATIONS INFORMATION

Figure 5. Adjustable Voltage Rails

Isolated Supply Adjustable Operation

The VCC2 isolated power rail is nominally 5V, but may be

overdrivenbyaddingtwoexternalresistors.Theunadjusted

output voltage represents the maximum for guaranteed

performance. Figure 5 illustrates configuration for VCC2

= 3.3V, V+ and V– are fixed at 5V and –5V respectively.

Channel Timing Uncertainty

Multiplechannelsaresupportedacrosstheisolationbound-

ary by encoding and decoding of the inputs and outputs.

Up to three signals in each direction are assembled as a

packet and transferred across the isolation barrier. The

time required to transfer all 3 bits is 100ns maximum,

and sets the limit for how often a signal can change on

the opposite side of the barrier. Encoding transmission is

independent for each data direction. The technique used

assigns SCK or SCL on the logic side, and SDO2 or I2 on

the isolated side, the highest priority such that there is

no jitter on the associated output channels, only delay.

This preemptive scheme will produce a certain amount of

uncertainty on the other isolation channels. The resulting

pulse width uncertainty on these low priority channels is

typically ±6ns, but may vary up to ±50ns if the low priority

channels are not encoded within the same high priority

serial packet.

Serial Peripheral Interface (SPI) Bus

The LTM2886-S provides a SPI compatible isolated inter-

face. The maximum data rate is a function of the inherent

channel propagation delays, channel to channel pulse

width uncertainty, and data direction requirements. Chan-

nel timing is detailed in Figures 6 through 9 and Tables

2 and 3. The SPI protocol supports four unique timing

configurations defined by the clock polarity (CPOL) and

clock phase (CPHA) summarized in Table 1.

Table 1. SPI Mode

CPOL CPHA

DATA TO (CLOCK) RELATIONSHIP

Sample (Rising)

Set-Up (Falling)

Set-Up (Rising)

Sample (Falling)

Set-Up (Rising)

Set-Up (Falling)

Sample (Rising)

The maximum data rate for bidirectional communication

is 4MHz, based on a synchronous system, as detailed in

the timing waveforms. Slightly higher data rates may be

achieved by skewing the clock duty cycle and minimiz-

ing the SDO to SCK set-up time, however the clock rate

is still dominated by the system propagation delays. A

discussion of the critical timing paths relative to Figures 6

and 7 follows.

The output adjustment range for VCC2 is 3V to 5.5V. VCC2

output voltage is calculated by:

VCC2 = 1.22V(1 + R2/R1)

The value of R1 should be no greater than 24.9k to mini-

mize errors in the output voltage caused by the AVCC2 pin

bias current.

Operation at low output voltages may result in thermal

shutdown due to low dropout regulator power dissipation.

42.2k

24.9k

2886 F05

SDOE

CS2

LTM2886-5S

VCC

GND

GND2

SDI

SDI2

SCK

SCK2

V–

AVCC2

V+

VCC2

SDO

DO2

SDO2

DO1

3.3V

–5V

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