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LTM2886 Datasheet(PDF) 23 Page - Analog Devices

Part # LTM2886
Description  SPI/Digital or I²C μModule Isolator with Fixed ±5V and Adjustable 5V Regulated Power
PDF  38 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM2886 Datasheet(HTML) 23 Page - Analog Devices

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LTM2886
23
Rev C
For more information www.analog.com/LTM2886
APPLICATIONS INFORMATION
Table 3. Unidirectional SPI Timing Event Description
TIME
CPHA
EVENT DESCRIPTION
t0
0, 1
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns
t0 to t1
0, 1
Propagation delay chip select, logic to isolated side
t2
0
Start of data transmission, data set-up
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
t2 to t3
0
Propagation delay of data, logic side to isolated side
1
Propagation delay of data and clock, logic side to isolated side
t3
0, 1
Logic side data sample time, half clock period delay from data set-up transition
t3 to t5
0, 1
Clock propagation delay, clock and data transition
t4 to t5
0, 1
Data to clock delay, must be ≤13ns
t5 to t6
0, 1
Clock to data delay, must be ≤3ns
t5 to t7
0, 1
Data and clock propagation delay
t8
0
Last clock and data transition
1
Last clock transition
t8 to t9
0
Clock and data propagation delay
1
Clock propagation delay
t9 to t10
1
Data propagation delay
t11
0, 1
Asynchronous chip select transition, end of transmission
t12
0, 1
Chip select transition isolated side
Figure 11. Isolated SDA2 Pin Schematic
Figure 10. I2C Timing Diagram
2886 F11
SDA2
1.8mA
FROM
LOGIC
SIDE
TO
LOGIC
SIDE
GLITCH FILTER
2886 F10
SDA
1
8
9
SDA2
SCL
SCL2
START
tPROP
tSU;DAT
tHD;DAT
tSU;ACK
SLAVE ACK
STOP
Additional proprietary circuitry monitors the slew rate on
the SDA and SDA2 signals to manage directional control
across the isolation barrier. Slew rates on both pins must
be greater than 1V/µs for proper operation.
The logic side bidirectional serial data pin, SDA, requires a
pull-up resistor or current source connected to VL. Follow
the requirements in Figures 12 and 13 for the appropri-
ate pull-up resistor on SDA that satisfies the desired rise
time specifications and VOL maximum limits for FAST and
STANDARD modes. The resistance curves represent the
maximum resistance boundary; any value may be used
to the left of the appropriate curve.



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