LPC1111FDH20SLASH002 datasheet(2/127 Pages) NXP

2 / 127 page

LPC111X

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Product data sheet

Rev. 9.2 — 26 March 2014

2 of 127

NXP Semiconductors

LPC1110/11/12/13/14/15

32-bit ARM Cortex-M0 microcontroller

 Digital peripherals:

 Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors. In addition, a configurable open-drain mode is supported on the

LPC1100L and LPC1100XL series.

 GPIO pins can be used as edge and level sensitive interrupt sources.

 High-current output driver (20 mA) on one pin.

 High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus (not on

LPC1112FDH20/102).

 Four general purpose counter/timers with up to eight capture inputs and up to 13

match outputs.

 Programmable WatchDog Timer (WDT) the LPC1100 series only.

 Programmable windowed WDT on the LPC1100L and LPC1100XL series only.

 Analog peripherals:

 10-bit ADC with input multiplexing among 5, 6, or 8 pins depending on package

size.

 Serial interfaces:

 UART with fractional baud rate generation, internal FIFO, and RS-485 support.

 Two SPI controllers with SSP features and with FIFO and multi-protocol

capabilities (second SPI on LPC1100 and LPC1100L series LQFP48 package

only).

 I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode (not on

LPC1112FDH20/102).

 Clock generation:

 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

 Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock.

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

 Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for any given application through one simple function

call. (LPC1100L and LPC1100XL series only.)

 Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

13 of the functional pins.

 Power-On Reset (POR).

 Brownout detect with up to four separate thresholds for interrupt and forced reset.

 Unique device serial number for identification.

 Single power supply (1.8 V to 3.6 V).

 Available as LQFP48 package, HVQFN33 package, and TFBGA48 package.

LPC1111FDH20/002 Datasheet(PDF) 2 Page - NXP Semiconductors

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