LPC1111FDH20SLASH002 datasheet(94/127 Pages) NXP

94 / 127 page

LPC111X

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Product data sheet

Rev. 9.2 — 26 March 2014

94 of 127

NXP Semiconductors

LPC1110/11/12/13/14/15

32-bit ARM Cortex-M0 microcontroller

11.7 SPI interfaces

[1]

Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2]

Tamb = 40 C to 105 C.

[3]

Tcy(clk) = 12  Tcy(PCLK).

[4]

Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.

Fig 46. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

Table 29.

Dynamic characteristics of SPI pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SPI master (in SPI mode)

Tcy(clk)

clock cycle time

full-duplex mode

[1]

when only transmitting [1]

tDS

data set-up time

in SPI mode

2.4 V

 V

DD  3.6 V

[2]

2.0 V

 V

DD < 2.4 V

[2]

1.8 V

 V

DD < 2.0 V

[2]

tDH

data hold time

in SPI mode

[2]

tv(Q)

data output valid time in SPI mode

[2]

th(Q)

data output hold time in SPI mode

[2]

SPI slave (in SPI mode)

Tcy(PCLK)

PCLK cycle time

tDS

data set-up time

in SPI mode

[3][4]

tDH

data hold time

in SPI mode

[3][4]

 T

cy(PCLK) + 4

tv(Q)

data output valid time in SPI mode

[3][4]

 T

cy(PCLK) + 11

th(Q)

data output hold time in SPI mode

[3][4]

 T

cy(PCLK) + 5

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