LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
22 of 70
NXP Semiconductors
LPC1766
Fast communication chip
• FullCAN messages can generate interrupts.
7.14 12-bit ADC
The LPC1766 contains one ADC. It is a single 12-bit successive approximation ADC with
eight channels and DMA support.
7.14.1 Features
• 12-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range Vi(VREFN) to Vi(VREFP).
• 12-bit conversion rate: 1 MHz.
• Individual channels can be selected for conversion.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or Timer Match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
• DMA support.
7.15 10-bit DAC
The DAC allows the LPC1766 to generate a variable analog output. The maximum output
value of the DAC is Vi(VREFP).
7.15.1 Features
• 10-bit DAC
• Resistor string architecture
• Buffered output
• Power-down mode
• Selectable output drive
• Dedicated conversion timer
• DMA support
7.16 UARTs
The LPC1766 each contain four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.16.1 Features
• 16 B Receive and Transmit FIFOs.
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