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LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
37 of 70
NXP Semiconductors
LPC1766
Fast communication chip
8.
Limiting values
[1]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
Including voltage on outputs in 3-state mode.
[3]
Not to exceed 4.6 V.
[4]
The peak current is limited to 25 times the corresponding maximum current.
[5]
Dependent on package type.
[6]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k
Ω series resistor.
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
VDD(3V3)
supply voltage (3.3 V)
core and external
rail
2.4
3.6
V
VREG(3V3)
Voltage regulator supply voltage (3.3 V)
2.4
3.6
V
VDDA
analog 3.3 V pad supply voltage
−0.5
+4.6
V
Vi(VBAT)
input voltage on pin VBAT
for the RTC
−0.5
+4.6
V
Vi(VREFP)
input voltage on pin VREFP
−0.5
+4.6
V
VIA
analog input voltage
on ADC related
pins
−0.5
+5.1
V
VI
input voltage
5 V tolerant I/O
pins; only valid
when the VDD(3V3)
supply voltage is
present
[2]
−0.5
+6.0
V
other I/O pins
[2][3]
−0.5
VDD(3V3) +
0.5
V
IDD
supply current
per supply pin
[4] -
100
mA
ISS
ground current
per ground pin
[4] -
100
mA
Ilatch
I/O latch-up current
−(0.5V
DD(3V3)) < VI
< (1.5VDD(3V3));
Tj < 125 °C
-
100
mA
Tstg
storage temperature
[5]
−40
+150
°C
Ptot(pack)
total power dissipation (per package)
based on package
heat transfer, not
device power
consumption
-1.5
W
Vesd
electrostatic discharge voltage
human body
model; all pins
[6]
−2000
+2000
V
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