49 / 70 page
LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
49 of 70
NXP Semiconductors
LPC1766
Fast communication chip
11.4 JTAG interface
[1]
Parameters are valid over operating temperature range unless otherwise specified.
11.5 I2C-bus
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25
°C), nominal supply voltages.
[3]
Bus capacitance Cb in pF, from 10 pF to 400 pF.
Table 12.
Dynamic characteristics of the JTAG clock source
Tamb = −40 °C to +85 °C for commercial applications; VDD(3V3) over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fTCK
TCK input frequency
-
-
CCLK
⁄
6
MHz
Table 13.
Dynamic characteristic: I2C-bus pins
Tamb = −40 °C to +85 °C for industrial applications; VDD(3V3) over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
I2C-bus pins (P0[27] and P0[28])
tf(o)
output fall time
VIH to VIL
20 + 0.1
× C
b
[3]
--
ns
tr
rise time
<tbd>
<tbd>
<tbd>
tf
fall time
<tbd>
<tbd>
<tbd>
tBUF
bus free time between a STOP and
START condition
-
<tbd>
<tbd>
<tbd>
tLOW
LOW period of the SCL clock
-
<tbd>
<tbd>
<tbd>
tHD;STA
hold time (repeated) START
condition
-
<tbd>
<tbd>
<tbd>
tHIGH
HIGH period of the SCL clock
-
<tbd>
<tbd>
<tbd>
tSU;DAT
data set-up time
-
<tbd>
<tbd>
<tbd>
tSU;STA
set-up time for a repeated START
condition
-
<tbd>
<tbd>
<tbd>
tSU;STO
set-up time for STOP condition
-
<tbd>
<tbd>
<tbd>
Fig 17. I2C-bus pins clock timing
P
SS
P
002aad985
tHD;STA
tBUF
tHD;STA
tSU;STA
tSU;DAT
tf
tHIGH
tSU;STO
tr
tHD;STA
tLOW
SDA
SCL
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