LPC1766 datasheet(43/70 Pages) ETC2

43 / 70 page

LPC1766_0.02

Objective data sheet

Rev. 00.02 — 12 August 2008

43 of 70

NXP Semiconductors

LPC1766

Fast communication chip

Conditions: active mode entered executing code from flash; core voltage 2.7 V; all peripherals

enabled but not configured to run.

Fig 8.

IREGact(3V3) at different temperatures (active mode)

Conditions: active mode entered executing code from flash; Tamb = 25 °C; RTC running;

Fig 9.

IBATact for different core voltages (active mode)

Table 7.

Typical peripheral current consumption

Core voltage 3.3 V; Tamb =25 °C; all measurements in μA; PCLK = CCLK⁄8; all peripherals enabled.

Peripheral

CCLK = 12 MHz

CCLK = 80 MHz

active mode

sleep mode

active mode

sleep mode

Timer0

<tbd>

Timer1

<tbd>

Timer2

<tbd>

Timer3

<tbd>

temperature (

°C)

−40

−15

002aad952

IREGact

(mA)

10 MHz

45 MHz

80 MHz

tbd

VREG(3V3) (V)

2.4

3.6

3.2

2.8

002aad953

0.8

0.7

0.9

IBATact

(

μA)

0.6

tbd

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