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LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
58 of 70
NXP Semiconductors
LPC1766
Fast communication chip
12. ADC electrical characteristics
[1]
Conditions: VSSA =0V, VDDA =3.3 V.
[2]
The ADC is monotonic, there are no missing codes.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 29.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 29.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 29.
[6]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 29.
[7]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 29.
[8]
See Figure 30.
Table 20.
ADC characteristics
VDDA = 2.7 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIA
analog input voltage
0
-
VDDA
V
Cia
analog input capacitance
-
-
<tbd>
pF
ED
differential linearity error
[1][2][3] -2
<tbd>
LSB
EL(adj)
integral non-linearity
[1][4] -1
<tbd>
LSB
EO
offset error
[1][5] -
-
<tbd>
LSB
EG
gain error
[1][6] --<tbd>
%
ET
absolute error
[1][7] -
-
<tbd>
LSB
Rvsi
voltage source interface
resistance
[8] --<tbd>
k
Ω
SRin
input slew rate
<tbd>
<tbd>
<tbd>
V/ms
Tcy(ADC)
ADC clock cycle
<tbd>
<tbd>
<tbd>
ns
tADC
conversion time
<tbd>
<tbd>
<tbd>
ns
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