LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
6 of 70
NXP Semiconductors
LPC1766
Fast communication chip
6.
Pinning information
6.1 Pinning
6.2 Pin description
Fig 2.
Pin configuration LQFP100 package
LPC176xFBD100
75
51
1
25
002aad945
Table 3.
Pin description
Symbol
Pin
Type
Description
P0[0] to P0[31]
I/O
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the pin connect
block. Pins 12, 13, 14, and 31 of this port are not available.
P0[0]/RD1/TXD3/
SDA1
46[1]
I/O
P0[0] — General purpose digital input/output pin.
I
RD1 — CAN1 receiver input.
O
TXD3 — Transmitter output for UART3.
I/O
SDA1 — I2C1 data input/output (this is not an I2C-bus compliant open-drain pin).
P0[1]/TD1/RXD3/
SCL1
47[1]
I/O
P0[1] — General purpose digital input/output pin.
O
TD1 — CAN1 transmitter output.
I
RXD3 — Receiver input for UART3.
I/O
SCL1 — I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin).
P0[2]/TXD0/AD0[7] 98[2]
I/O
P0[2] — General purpose digital input/output pin.
O
TXD0 — Transmitter output for UART0.
I
AD0[7] — A/D converter 0, input 7.
P0[3]/RXD0/AD0[6] 99[2]
I/O
P0[3] — General purpose digital input/output pin.
I
RXD0 — Receiver input for UART0.
I
AD0[6] — A/D converter 0, input 6.
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
81[1]
I/O
P0[4] — General purpose digital input/output pin.
I/O
I2SRX_CLK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
I
RD2 — CAN2 receiver input.
I
CAP2[0] — Capture input for Timer 2, channel 0.
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