LPC1766 datasheet(44/70 Pages) ETC2

44 / 70 page

LPC1766_0.02

Objective data sheet

Rev. 00.02 — 12 August 2008

44 of 70

NXP Semiconductors

LPC1766

Fast communication chip

RIT

<tbd>

UART0

<tbd>

UART1

<tbd>

UART2

<tbd>

UART3

<tbd>

PWM1

<tbd>

Motor control

PWM

<tbd>

Quadrature

encoder

<tbd>

I2C0-bus

<tbd>

I2C1-bus

<tbd>

I2C2-bus

<tbd>

SPI

<tbd>

SSP0

<tbd>

SSP1

<tbd>

CAN1

<tbd>

CAN2

<tbd>

ADC

<tbd>

DAC

<tbd>

USB

<tbd>

Ethernet

<tbd>

GPDMA controller <tbd>

<tbd>

Table 7.

Typical peripheral current consumption …continued

Core voltage 3.3 V; Tamb =25 °C; all measurements in μA; PCLK = CCLK⁄8; all peripherals enabled.

Peripheral

CCLK = 12 MHz

CCLK = 80 MHz

active mode

sleep mode

active mode

sleep mode

Table 8.

Typical RTC power consumption

VBAT = 3.3 V; Tamb =25 °C; all measurements in μA; RTC clock = 1 Hz; VREG not present.

Power modes

active

sleep

deep-sleep

power-down

deep

power-down

IBAT in μA

<tbd>

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