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HD404374FT Datasheet(PDF) 37 Page - Renesas Technology Corp |
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HD404374FT Datasheet(HTML) 37 Page - Renesas Technology Corp |
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37 / 161 page  HD404374/HD404384/HD404389/HD404082/HD404084 Series Rev.5.00, Sep.11.2003, page 37 of 161 Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit WU WU WU WU 0 INT INT INT INT 0 Timer A Timer B Timer C A/D or Serial IE 1 1 1 1 1 1 IFWU• IMWU 1 0 0 0 0 0 IF0• IM0 * 1 0 0 0 0 IFTA• IMTA * * 1 0 0 0 IFTB• IMTB * * * 1 0 0 IFTC• IMTC * * * * 1 0 IFAD• IMAD+IFS•IMS * * * * * 1 Note: * Operation is not affected whether the value is 0 or 1. 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Save to stack IE reset Execution of JMPL instruction at vector address Save to stack Vector address generated Execution of instruction at start address of interrupt routine Instruction cycle Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction. Figure 9 Interrupt Sequence |
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