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HD404374FT Datasheet(PDF) 97 Page - Renesas Technology Corp |
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HD404374FT Datasheet(HTML) 97 Page - Renesas Technology Corp |
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97 / 161 page ![]() HD404374/HD404384/HD404389/HD404082/HD404084 Series Rev.5.00, Sep.11.2003, page 97 of 161 Transfer end (IFS ←"1") Disable interrupts IFS ←"0" SMR1 write IFS=1? Normal termination Serial clock error processing (1) Serial clock error detection flowchart Serial clock wait state Transfer state Serial clock wait state Transfer state (Noise) State SCK pin (input) SMR1 write IFS 12 3 4 5 6 7 8 (2) Serial clock error detection sequence Flag set by octal counter reaching 000 Flag reset by transfer end processing Yes No Because the serial interface returns to the transfer state, a write to SMR1 resets IFS. Figure 55 Example of Serial Clock Error Detection |
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