HD404374FT datasheet(60/161 Pages) RENESAS

60 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 60 of 161

Table 22

Programmable I/O Circuits

MIS3 (bit 3 of MIS)

DCD,DCR

PDR

PMOS

—

CMOS buffer

NMOS

—

Pull-up MOS

—

Note:

— : OFF

Table 23 Circuit Configurations of I/O Pins

Type

Circuit Configuration

Pins

VCC

Input control signal

MIS3

DCD, DCR

PDR

Pull-up control signal

Buffer control signal

Output data

Input data

0-D9

0, R13

0, R21

VCC

Input control signal

MIS3

DCR

PDR

Pull-up control signal

Buffer control signal

Output data

Input data

SMR22

0–R73

I/O pins

VCC

Input control signal

Pull-up control signal

Buffer control signal

Output data

A/D input

A/D channel control signal

Input data

MIS3

DCR

PDR

0-R73

0-AN3

Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state

and peripheral function selections are cleared.

1. Applies to HD404374, HD404384, and HD404389 Series.

2. Applies to HD404082 and HD404084 Series.

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