HD404374FT datasheet(70/161 Pages) RENESAS

70 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 70 of 161

1/4

1/2

32.768-kHz

oscillator

System

clock

Data bus

Clock line

Signal line

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

1/2 t Wcyc

t Wcyc

øPER

HD404374 Series

Figure 32 Timer A Block Diagram

Timer A Operation

Free-running timer operation:

The timer A input clock is selected by timer mode register A (TMA: $00F).

Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input

clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value

becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer

A continues counting up after the count value returns to $00, so that an interrupt is generated regularly

every 256 input clock cycles.

Realtime clock time base operation (HD404374 Series):

Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1.

As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using

the 32.768 kHz crystal oscillator as the basic clock.

When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00

by the program.

HD404374FT Datasheet(PDF) 70 Page - Renesas Technology Corp

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