HD404374FT datasheet(56/161 Pages) RENESAS

56 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 56 of 161

System clock select register (SSR: $004)

Make sure to set bit 3 of the system clock select register to 1 if the HD404374 series is being used without

the subsystem clock, and on the HD404384, HD404389, HD404082, and HD404084 series. The microcomputer

will malfunction if the setting is not 1.

Bit

Read/Write

Initial value on reset

Bit name

SSR3

SSR2*

SSR1*

SSR0

System clock division ratio switch

Division-by-4 (fcyc - fOSC/4)

Division-by-32 (fcyc - fOSC/32)

System clock division ratio switch

fosc=0.4–1.0MHz

fosc=1.6–8.5MHz

Subsystem clock division ratio switch

fSUB=fx/8

fSUB=fx/4

(HD404374 Series)

Subsystem clock operates in stop mode

Subsystem clock stops in stop mode

Note: * Applies to HD404374 Series.

The CR oscillation frequency differs depending on the operating voltage and resistance value.

Set SSR1 to match the operating frequency. Note that if the frequency being used does not

match the SSR1 setting, subsystems using the 32.768 kHz oscillation frequency will not

operate correctly.

Subsystem clock stop setting

This bit must be set to 1 following power-on and reset if the HD404374 series is being

used without the subsystem clock, and on the HD404384, HD404389, HD404082, and

HD404084 series. If it is set to 0 (the initial value), malfunctioning may occur in the stop

mode.

Figure 22 System Clock Select Register

HD404374FT Datasheet(PDF) 56 Page - Renesas Technology Corp