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HD404374FT Datasheet(PDF) 75 Page - Renesas Technology Corp |
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HD404374FT Datasheet(HTML) 75 Page - Renesas Technology Corp |
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75 / 161 page  HD404374/HD404384/HD404389/HD404082/HD404084 Series Rev.5.00, Sep.11.2003, page 75 of 161 (1) Toggle output waveform (timer B, timer C) (2) PWM output waveform (timer B, timer C) ( ) 256 clock periods 256 clock periods Free-running timer (256 – N) clock periods (256 – N) clock periods Reload timer T (N + 1) T 256 T T (256 – N) TMB13 = 0 TMC13 = 0 (free-running timer) × × × TMB13 = 1 TMC13 = 1 (reload timer) Notes: T: Counter input clock period The clock input source and division ratio are controlled by timer mode register B1 and timer mode register C1. N: Value in timer write register B or timer write register C When N = 255 (= $FF), PWM output is always fixed at the timer low level.) Figure 35 Timer Output Waveforms |
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