HD404374FT datasheet(92/161 Pages) RENESAS

92 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 92 of 161

Serial interface operating states:

The serial interface has the operating states shown in figure 53 in external clock mode and internal clock

mode.

STS instruction wait state

Serial clock wait state

Transfer state

Clock continuous output state (internal clock mode only)

• STS instruction wait state

Upon MCU reset ((00) and (10) in figure 53), the serial interface enters the STS instruction wait state.

In the STS instruction wait state, the internal state of the serial interface is initialized. Even if the serial

clock is input at this time, the serial interface will not operate. When the STS instruction is executed

((01), (11)), the serial interface enters the serial clock wait state.

• Serial clock wait state

The serial clock wait state is the interval from STS instruction execution until the first serial clock

falling edge. When the serial clock is input in the serial clock wait state ((02), (12)), the octal counter

begins counting, the contents of the serial data register (SRL, SRU) begin shifting, and the serial

interface enters the transfer state. However, if clock continuous output mode is selected in internal

clock mode, the serial interface enters the clock continuous output state ((17)) instead of the transfer

state.

If a write to serial mode register 1 (SMR1) is performed in the serial clock wait state, the serial interface

enters the STS instruction wait state ((04), (14)).

• Transfer state

The transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising

edge. In the transfer state, if an STS instruction is executed or if eight serial clocks have been input, the

octal counter is cleared to 000, and the serial interface makes a state transition. If an STS instruction is

executed ((05), (15)), the serial interface enters the serial clock wait state. After eight serial clocks have

been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and

enters the STS instruction wait state ((13)) when in internal clock mode.

In internal clock mode, the serial clock stops after output of eight clocks.

If a write to serial mode register 1 (SMR1) is performed in the transfer state ((06), (16)), the serial

interface is initialized and enters the STS instruction wait state.

When the serial interface switches from the transfer state to another state, the octal counter is reset to

000 and the serial interrupt request flag (IFS) is set.

• Clock continuous output state (internal clock mode only)

In the clock continuous output state, no receive or transmit operation is performed, and the serial clock

is only output from the

SCK pin. It is therefore effective in internal clock mode.

If the serial clock is input ((17)) when bit 3 (PMR33) of port mode register 3 (PMR3) is cleared to 0 and

the serial interface is in the serial clock wait state, a transition is made to the clock continuous output

state.

If a write to serial mode register 1 (SMR1) is performed in the clock continuous output state ((18)), the

serial interface enters the STS instruction wait state.

HD404374FT Datasheet(PDF) 92 Page - Renesas Technology Corp

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