HD404374FT datasheet(91/161 Pages) RENESAS

91 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 91 of 161

Serial Interface Operation

Selecting and changing serial interface operating mode:

The operating modes that can be selected for the serial interface are shown in table 26. The combination of

port mode register 3 (PMR3) values should be selected from this table. When the serial interface operating

mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1

(SMR1).

Note : The serial interface is initialized by writing to serial mode register 1 (SMR1: $024). See figure 56

Serial Mode Register 1, for details.

Table 26

Serial Interface Operating Modes

PMR3

Bit3

Bit2

Bit1

Serial interface operating mode

Clock continuous output mode

Receive mode

Transmit mode

Note : * Don't care

Serial interface pin setting:

The R2

1/SCK pin and R22/SI/SO pin are set by writing data to port mode register 3 (PMR3).

See Serial

Interface Registers, for details.

Serial clock source setting:

The serial clock is set by writing data to serial mode register 1 (SMR1). See Serial Interface Registers, for

details.

Serial data setting:

Transmit serial data is set by writing data to the serial data register (SRL, SRU).

Receive serial data is obtained by reading the serial data register (SRL, SRU). Serial data is shifted by

means of the serial clock to perform input/output from/to an external device.

The output level of the SO pin is undetermined until the first data is output after a reset by the MCU, or

until high/low control is performed in the idle state.

Transfer control:

Serial interface operation is started by an STS instruction. The octal counter is reset to 000 by the STS

instruction, and is incremented by 1 on each rise of the serial clock. When 8 serial clock pulses have been

input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial

interrupt request flag (IFS) is set, and transfer is terminated.

The serial clock is selected by means of serial mode register 1 (SMR1). See figure 56.

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