HD404374FT datasheet(55/161 Pages) RENESAS

55 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 55 of 161

System Clock Gear Function

The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be

selected by software for the instruction execution time. Efficient power consumption can be achieved by

operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at

the other times. Figure 21 shows the system clock conversion method.

System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the

division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to

distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction.

When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is

entered. In this case a transition is made to standby mode for the duration of the gear conversion, but after

the synchronization time has elapsed, a transition is made automatically to active mode. As soon as the

transition is made to active mode, the gear enable flag is reset.

The same procedure is used for conversion from division-by-32 to division-by-4.

Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may

result if an interrupt is generated during gear conversion.

Division-by-32 setting (SSR0 = 1)

Set gear enable flag

Execute SBY instruction

Execute next instruction

Synchronization time

Division-by-4 setting (SSR0 = 0)

Set gear enable flag

Execute SBY instruction

Execute next instruction

Synchronization time

Figure 21 System Clock Division Ratio Conversion Flowchart

HD404374FT Datasheet(PDF) 55 Page - Renesas Technology Corp