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HD404374FT Datasheet(PDF) 61 Page - Renesas Technology Corp |
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HD404374FT Datasheet(HTML) 61 Page - Renesas Technology Corp |
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61 / 161 page ![]() HD404374/HD404384/HD404389/HD404082/HD404084 Series Rev.5.00, Sep.11.2003, page 61 of 161 Table 23 Circuit Configurations of I/O Pins (cont) Type Circuit Configuration Pins I/O pins VCC VCC MIS3 PDR Pull-up control signal I/O control signal Output data Input data SCK SCK VCC VCC MIS3 PDR Pull-up control signal PMOS control signal Output data SMR22 SO SO Output pins VCC VCC MIS3 PDR Pull-up control signal Output data TOB, TOC TOB, TOC RESET Input data RESET VCC MIS3 PDR 0 etc. WU 0, INT0, EVNB, SI Perip- heral function pins Input pins A/D Input A/D channel control signal AN 4, AN5 *1 Note: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. Applies to HD404389 Series. |
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