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4518 Datasheet(PDF) 111 Page - Renesas Technology Corp |
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4518 Datasheet(HTML) 111 Page - Renesas Technology Corp |
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111 / 160 page ![]() Skip condition Number of cycles Number of words Instruction code D9 D0 Flag CY 2 16 Skip condition Number of cycles Number of words Instruction code D9 D0 Flag CY 2 16 Skip condition Number of cycles Number of words Instruction code D9 D0 Flag CY 2 16 Skip condition Number of cycles Number of words Instruction code D9 D0 Flag CY 2 16 Rev.3.01 2005.06.15 page 111 of 157 REJ03B0008-0301 4518 Group TAD (Transfer data to Accumulator from register D) 0001010001 051 11 – – Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Note: When this instruction is executed, “0” is stored to the bit 3 (A3) of register A. Operation: (A2–A0) ← (DR2–DR0) (A3) ← 0 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TABPS (Transfer data to Accumulator and register B from PreScaler) TABSI (Transfer data to Accumulator and register B from register SI) 1001111000 278 11 – – Grouping: Serial I/O operation Description: Transfers the high-order 4 bits (SI7–SI4) of serial I/O register SI to register B, and transfers the low-order 4 bits (SI3–SI0) of serial I/O register SI to register A. Operation: (B) ← (SI7–SI4) (A) ← (SI3–SI0) 1001110101 275 11 – – Grouping: Timer operation Description: Transfers the high-order 4 bits (TPS7– TPS4) of prescaler to register B, and transfers the low-order 4 bits (TPS3–TPS0) of prescaler to register A. Operation: (B) ← (TPS7–TPS4) (A) ← (TPS3–TPS0) TADAB (Transfer data to register AD from Accumulator from register B) 1000111001 239 11 – – Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), this in- struction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), trans- fers the contents of register B to the high-order 4 bits (AD7–AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of compara- tor register. (Q13 = bit 3 of A/D control register Q1) Operation: (AD7–AD4) ← (B) (AD3–AD0) ← (A) |
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