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4518 Datasheet(PDF) 110 Page - Renesas Technology Corp

Part # 4518
Description  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  160 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4518 Datasheet(HTML) 110 Page - Renesas Technology Corp

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Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.3.01
2005.06.15
page 110 of 157
REJ03B0008-0301
4518 Group
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
0010p5
p4
p3
p2
p1
p0
0p
13
–
–
Grouping:
Arithmetic operation
Operation:
(SP)
← (SP) + 1
(SK(SP))
← (PC)
(PCH)
← p
(PCL)
← (DR2–DR0, A3–A0)
(DR2)
← 0
(DR1, DR0)
← (ROM(PC))9, 8
(B)
← (ROM(PC))7–4
(A)
← (ROM(PC))3–0
(PC)
← (SK(SP))
(SP)
← (SP) – 1
8
+p
Description: Transfers bits 9 and 8 to register D, bits 7 to 4
to register B and bits 3 to 0 to register A.
These bits 7 to 0 are the ROM pattern in ad-
dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
by registers A and D in page p.
Note: p is 0 to 15 for M34518M2, and p is 0 to 31 for
M34518M6, p is 0 to 47 for M34518M6, and p is 0 to
63 for M34518M8E8.
When this instruction is executed, be careful not to over
the stack because 1 stage of stack register is used.
TABE (Transfer data to Accumulator and register B from register E)
0000101010
02A
11
––
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
Operation:
(B)
← (E7–E4)
(A)
← (E3–E0)
TABAD (Transfer data to Accumulator and register B from register AD)
1001111001
279
11
––
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), trans-
fers the high-order 4 bits (AD9–AD6) of
register AD to register B, and the middle-or-
der 4 bits (AD5–AD2) of register AD to
register A. In the comparator mode (Q13 = 1),
transfers the middle-order 4 bits (AD7–AD4)
of register AD to register B, and the low-order
4 bits (AD3–AD0) of register AD to register A.
Operation:
In A/D conversion mode (Q13 = 0),
(B)
← (AD9–AD6)
(A)
← (AD5–AD2)
In comparator mode (Q13 = 1),
(B)
← (AD7–AD4)
(A)
← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
TAB4 (Transfer data to Accumulator and register B from timer 4)
1001110011
273
11
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T47–T44) of
timer 4 to register B.
Transfers the low-order 4 bits (T43–T40) of
timer 4 to register A.
Operation:
(B)
← (T47–T44)
(A)
← (T43–T40)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)



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