7512 datasheet(63/87 Pages) RENESAS

63 / 87 page

Feb 18, 2005

page 63 of 85

REJ03B0122-0101

7512 Group

Fig. 70 Structure of flash memory control register 1

Figure 70 shows the flash memory control register 1.

Bit 0 is erase suspend enable bit, and setting this bit “1” erase

suspend mode which makes erase operation interrupt briefly dur-

ing erase operation. To set this bit to “1”, it is necessary to write “0”

and then write “1” in succession. This bit can be set to “0” by only

writing “0”.

Bit 1 is erase suspend request bit. Writing this bit “1” when the

Flash memory control register 1

(0FE116, Initial 4016)

FMCR1

Erase suspend enable bit (Note 1)

0 : Erase suspend invalid

1 : Erase suspend valid

Erase suspend request bit (Note 2)

0 : Resume erase operation (No request)

1 : Interrupt erase operation (Requested)

Not used (“0” at write)

Erase suspend flag

0 : Executing erase operation

1 : Suspending erase operation (Erase suspend mode)

Not used (“0” at write)

Note 1 To set this bit “1”, write “0” and then write “1” in succession. To reset

this bit “0”, only write “0”.

2 This bit is valid only when erase suspend enable bit is “1”.

erase suspend enable bit is “1”, erase operation is interrupted.

Bit 6 is erase suspend flag, and becomes “0” during erase opera-

tion.

Figure 71 shows flash memory control register 2.

Bit 1 is EW1 mode select bit. Setting this bit “1”, EW1 mode be-

comes available.

Bit 4 is All user block E/W enable bit.

Fig. 71 Structure of flash memory control register 2

Table. 15 Specification of E/W protect

All user block

E/W enable bit

8KB user block

E/W enable bit

8 KBX2 block

Addresses C00016 to FFFF16

Protect

Enable

16 KBX2 block

Addresses 400016 to BFFF16

Protect

Enable

Data block

Addresses 100016 to 1FFF16

Enable

Flash memory control register 2

(0FE216, Initial 4516)

FMCR2

Reserved (returns unknown when read)

EW1 mode select bit (Note 1, 3)

0 : E/W0 mode

1 : E/W1 mode

Reserved (returns unknown when read)

All user block E/W enable bit (Note 1, 2)

0 : E/W prohibit

1 : E/W enable

Reserved (“0” at write, returns “0” at read)

Not used (Indefinite at read)

Not used (returns “0” at read)

Note 1 To set this bit “1”, it is necessary to write “0” and then write “1” in

succession. This bit can be set to “0” by only writing “0”.

Note 2 This bit can be written only CPU rewrite mode selection bit “1”.

Note 3 Setting this bit “1” must be done at CPU rewrite mode select bit is “1”.

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