7512 datasheet(28/87 Pages) RENESAS

28 / 87 page

Feb 18, 2005

page 28 of 85

REJ03B0122-0101

7512 Group

[I2C Data Shift Register (S0)] 002B16

The I2C data shift register (S0 : address 002B16) is an 8-bit shift

When transmit data is written into this register, it is transferred to

the outside from bit 7 in synchronization with the SCL clock, and

each time one-bit data is output, the data of this register are

shifted by one bit to the left. When data is received, it is input to

this register from bit 0 in synchronization with the SCL clock, and

each time one-bit data is input, the data of this register are shifted

by one bit to the left. The minimum 2 machine cycles are required

from the rising of the SCL clock until input to this register.

The I2C data shift register is in a write enable status only when the

I2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of

the I2C control register is “1”. The bit counter is reset by a write in-

struction to the I2C data shift register. When both the ES0 bit and

the MST bit of the I2C status register (address 002D16) are “1”, the

SCL is output by a write instruction to the I2C data shift register.

Reading data from the I2C data shift register is always enabled re-

gardless of the ES0 bit value.

[I2C Address Register (S0D)] 002C16

The I2C address register (address 002C16) consists of a 7-bit

slave address and a read/write bit. In the addressing mode, the

slave address written in this register is compared with the address

data to be received immediately after the START condition is de-

tected.

•Bit 0: Read/write bit (RWB)

This is not used in the 7-bit addressing mode. In the 10-bit ad-

dressing mode, the first address data to be received is compared

with the contents (SAD6 to SAD0 + RWB) of the I2C address reg-

ister.

The RWB bit is cleared to “0” automatically when the stop condi-

tion is detected.

•Bits 1 to 7: Slave address (SAD0–SAD6)

These bits store slave addresses. Regardless of the 7-bit address-

ing mode or the 10-bit addressing mode, the address data

transmitted from the master is compared with these bit's contents.

Fig. 27 Structure of I2C address register

SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB

Slave address

I2C address register

(S0D: address 002C 16)

Read/write bit

7512 Datasheet(PDF) 28 Page - Renesas Technology Corp

7512 Datasheet(HTML) 28 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL