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SH7136 Datasheet(PDF) 37 Page - Renesas Technology Corp |
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SH7136 Datasheet(HTML) 37 Page - Renesas Technology Corp |
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37 / 1160 page ![]() Section 1 Overview Rev. 2.00 Sep. 10, 2008 Page 11 of 1130 REJ09B0402-0200 Classification Symbol I/O Name Function MD1, MD0 I Mode set Sets the operating mode. Do not change values on these pins during operation. Only MD1 is available in the SH7136. Operating mode control FWE I Flash memory write enable Pin for flash memory Flash memory can be protected against programming or erasure through this pin. RES I Power-on reset When low, this LSI enters the power- on reset state. MRES I Manual reset When low, this LSI enters the manual reset state. WDTOVF O Watchdog timer overflow Output signal for the watchdog timer overflow Use a resistor of 1 M Ω or more when this pin needs to be pulled down. BREQ I Bus-mastership request Low when an external device requests the release of the bus mastership. This pin is available only on the SH7137. System control BACK O Bus-mastership request acknowledge Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus. This pin is available only on the SH7137. |
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