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SH7136 Datasheet(PDF) 87 Page - Renesas Technology Corp |
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SH7136 Datasheet(HTML) 87 Page - Renesas Technology Corp |
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87 / 1160 page ![]() Section 4 Clock Pulse Generator (CPG) Rev. 2.00 Sep. 10, 2008 Page 61 of 1130 REJ09B0402-0200 Table 4.4 Frequency Division Ratios Specifiable with FRQCR FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz)* PLL Multipli- cation Ratio I φ B φ P φ MI φ MPφ Iφ B φ P φ MI φ MPφ Input Clock I φ B φ P φ MI φ MPφ ×8 1/8 1/8 1/8 1/8 1/8 1 1 1 1 1 10 10 10 10 10 10 1/4 1/8 1/8 1/8 1/8 2 1 1 1 1 20 10 10 10 10 1/4 1/8 1/8 1/4 1/8 2 1 1 2 1 20 10 10 20 10 1/4 1/4 1/8 1/8 1/8 2 2 1 1 1 20 20 10 10 10 1/4 1/4 1/8 1/4 1/8 2 2 1 2 1 20 20 10 20 10 1/4 1/4 1/8 1/4 1/4 2 2 1 2 2 20 20 10 20 20 1/4 1/4 1/4 1/4 1/4 2 2 2 2 2 20 20 20 20 20 1/3 1/3 1/3 1/3 1/3 8/3 8/3 8/3 8/3 8/3 26 26 26 26 26 1/2 1/8 1/8 1/8 1/8 4 1 1 1 1 40 10 10 10 10 1/2 1/8 1/8 1/4 1/8 4 1 1 2 1 40 10 10 20 10 1/2 1/8 1/8 1/2 1/8 4 1 1 4 1 40 10 10 40 10 1/2 1/4 1/8 1/8 1/8 4 2 1 1 1 40 20 10 10 10 1/2 1/4 1/8 1/4 1/8 4 2 1 2 1 40 20 10 20 10 1/2 1/4 1/8 1/4 1/4 4 2 1 2 2 40 20 10 20 20 1/2 1/4 1/8 1/2 1/8 4 2 1 4 1 40 20 10 40 10 1/2 1/4 1/8 1/2 1/4 4 2 1 4 2 40 20 10 40 20 1/2 1/4 1/4 1/4 1/4 4 2 2 2 2 40 20 20 20 20 1/2 1/4 1/4 1/2 1/4 4 2 2 4 2 40 20 20 40 20 1/2 1/2 1/8 1/8 1/8 4 4 1 1 1 40 40 10 10 10 1/2 1/2 1/8 1/4 1/8 4 4 1 2 1 40 40 10 20 10 1/2 1/2 1/8 1/4 1/4 4 4 1 2 2 40 40 10 20 20 1/2 1/2 1/8 1/2 1/8 4 4 1 4 1 40 40 10 40 10 1/2 1/2 1/8 1/2 1/4 4 4 1 4 2 40 40 10 40 20 1/2 1/2 1/8 1/2 1/2 4 4 1 4 4 40 40 10 40 40 1/2 1/2 1/4 1/4 1/4 4 4 2 2 2 40 40 20 20 20 1/2 1/2 1/4 1/2 1/4 4 4 2 4 2 40 40 20 40 20 1/2 1/2 1/4 1/2 1/2 4 4 2 4 4 40 40 20 40 40 |
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