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SH7136 Datasheet(PDF) 38 Page - Renesas Technology Corp |
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SH7136 Datasheet(HTML) 38 Page - Renesas Technology Corp |
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38 / 1160 page ![]() Section 1 Overview Rev. 2.00 Sep. 10, 2008 Page 12 of 1130 REJ09B0402-0200 Classification Symbol I/O Name Function NMI I Non-maskable interrupt Non-maskable interrupt request pin Fix to high or low level when not in use. Interrupts IRQ3 to IRQ0 I Interrupt requests 3 to 0 Maskable interrupt request pin Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. IRQOUT O Interrupt request output Shows that an interrupt cause has occurred. The interrupt cause can be recognized even in the bus release state. Address bus A19 to A0 O Address bus Outputs addresses. This pin is available only on the SH7137. Data bus D7 to D0 I/O Data bus 8-bit bidirectional bus. This pin is available only on the SH7137. CS1, CS0 O Chip select 1 and 0 Chip-select signal for external memory or devices. This pin is available only on the SH7137. Bus control RD O Read Indicates reading of data from external devices. This pin is available only on the SH7137. WRL O Write Indicates a write access to bits 7 to 0 of the external data. This pin is available only on the SH7137. WAIT I Wait Input signal for inserting a wait cycle into the bus cycles during access to the external space. This pin is available only on the SH7137. TCLKA, TCLKB, TCLKC, TCLKD I MTU2 timer clock input External clock input pins for the timer Multi function timer- pulse unit 2 (MTU2) TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O MTU2 input capture/output compare (channel 0) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins |
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