SH7136 datasheet(72/1160 Pages) RENESAS

72 / 1160 page

Section 2 CPU

Rev. 2.00 Sep. 10, 2008 Page 46 of 1130

REJ09B0402-0200

2.6

Processing States

The CPU has the five processing states: reset, exception handling, bus release, program execution,

and power-down. Figure 2.4 shows the CPU state transition.

From any state

when

RES = 0

From any state except

deep software standby mode

when

RES = 1 and MRES = 0

Power-on reset state

Manual reset state

RES = 0

Reset state

RES = 1

RES = 1,

MRES = 1

When internal power-on reset by WDT

or internal manual reset by WDT occurs.

Exception

handling state

Exception

processing

source

occurs

Exception

processing

ends

Program

execution state

NMI interrupt or IRQ

interrupt occurs

Bus release state

Bus request

generated

Bus request

cleared

Bus request

generated

Bus request

cleared

Bus request

generated

Bus request

cleared

Sleep mode

SSBY bit = 1 and

STBYMD bit = 1

for SLEEP

instruction

SSBY bit = 1 and

STBYMD bit = 0

for SLEEP

instruction

SSBY bit = 0

for SLEEP

instruction

Software

standby mode

Power-down mode

Deep software

standby mode

Figure 2.4 Transitions between Processing States

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