SH7136 datasheet(91/1160 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 10, 2008 Page 65 of 1130

REJ09B0402-0200

4.4

The CPG has the following registers.

For details on the addresses of these registers and the states of these registers in each processing

state, see section 25, List of Registers.

Table 4.5

Abbrevia-

tion

R/W

Initial Value

Address

Access Size

Frequency control register

FRQCR

R/W

H'36DB

H'FFFFE800

Oscillation stop detection

control register

OSCCR

R/W

H'00

H'FFFFE814

4.4.1

Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the

internal clock (I

φ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock

(MP

φ). FRQCR can be accessed only in words.

FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT

overflow).

Bit:

Initial value:

R/W:

987654321

0011011011011011

R/W

IFC[2:0]

BFC[2:0]

PFC[2:0]

MIFC[2:0]

MPFC[2:0]

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