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SH7136 Datasheet(PDF) 82 Page - Renesas Technology Corp |
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SH7136 Datasheet(HTML) 82 Page - Renesas Technology Corp |
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82 / 1160 page ![]() Section 4 Clock Pulse Generator (CPG) Rev. 2.00 Sep. 10, 2008 Page 56 of 1130 REJ09B0402-0200 Figure 4.1 shows a block diagram of the clock pulse generator. CK PLL circuit ( ×8) Oscillator unit Internal clock (I φ) Internal bus Bus interface FRQCR: OSCCR: STBCR1: STBCR2: STBCR3: STBCR4: STBCR5: STBCR6: Frequency control register Oscillation stop detection control register Standby control register 1 Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 Standby control register 6 Peripheral clock (P φ) Bus clock (B φ = CK) EXTAL XTAL FRQCR OSCCR STBCR2 STBCR1 STBCR3 STBCR4 STBCR5 STBCR6 CPG control unit MTU2 clock (MP φ) MTU2S clock (MI φ) Clock frequency control circuit Standby control circuit [Legend] ×1 ×1/2 ×1/3 ×1/4 ×1/8 Divider Oscillation stop detection Oscillation stop detection circuit Crystal oscillator Figure 4.1 Block Diagram of Clock Pulse Generator |
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