SH7136 datasheet(33/1160 Pages) RENESAS

33 / 1160 page

Section 1 Overview

Rev. 2.00 Sep. 10, 2008 Page 7 of 1130

REJ09B0402-0200

1.2

Block Diagram

The block diagram of SH7136 and SH7137 is shown in figure 1.1.

SH2

CPU

UBC

I/O

port

(PFC)

[Legend]

ROM:

RAM:

UBC:

INTC:

CPG:

WDT:

CPU:

BSC:

DTC:

PFC:

MTU2:

MTU2S:

POE:

SCI:

SSU:

CMT:

ADC:

RCAN-ET:

I2C2:

H-UDI:

INTC

WDT

CPG

Peripheral bus (P

φ)

I bus (B

φ)

L bus (I

φ)

MTU2

MTU2S

POE

SSU

CMT

Power-

down

mode

control

External bus

Peripheral bus

controller

On-chip ROM

On-chip RAM

User break controller

Interrupt controller

Clock pulse generator

Watchdog timer

Central processing unit

Bus state controller

Data transfer controller

Pin function controller

Multi-function timer pulse unit 2

Multi-function timer pulse unit 2 (subset)

Port output enable

Serial communication interface

Synchronous serial communication unit

Compare match timer

A/D converter

Controller area network

I2C Bus interface 2

User debugging interface

Internal bus

controller

RAM

ROM

SCI

ADC

RCAN-ET

H-UDI

I2C2

BSC

DTC

Figure 1.1 Block Diagram

SH7136 Datasheet(PDF) 33 Page - Renesas Technology Corp

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