SH7136 datasheet(95/1160 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 10, 2008 Page 69 of 1130

REJ09B0402-0200

4.5

Changing Frequency

Selecting division ratios for the frequency divider can change the frequencies of the internal clock

φ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock (MPφ). This is

controlled by software through the frequency control register (FRQCR). The following describes

how to specify the frequencies.

1. In the initial state, IFC2 to IFC0 = H'011 (

×1/4), BFC2 to BFC0 = H'011 (×1/4), PFC2 to

PFC0 = H'011 (

×1/4), MIFC2 to MIFC0 = H'011 (×1/4), and MPFC2 to MPFC0 = H'011

(

×1/4).

2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM.

3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, MIFC2 to MIFC0,

and MPFC2 to MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed

×8, the frequencies are determined only be selecting division ratios. When specifying the

frequencies, satisfy the following condition: internal clock (I

φ) ≥ bus clock (Bφ) ≥ peripheral

clock (P

φ). When using the MTU2S clock and MTU2 clock, specify the frequencies to satisfy

the following condition: internal clock (I

φ) ≥ MTU2S clock (MIφ) ≥ MTU2 clock (MPφ) ≥

peripheral clock (P

φ) and bus clock (Bφ) ≥ MTU2 clock (MPφ). Code to rewrite values of

FRQCR should be executed in the on-chip ROM or on-chip RAM.

4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will

change after (1 to 24n) cyc + 11B

φ + 7Pφ.

n: Division ratio specified by the BFC bit in FRQCR (1, 1/2, 1/3, 1/4, or 1/8)

cyc: Clock obtained by dividing EXTAL by 8 with the PLL.

Note:

(1 to 24n) depends on the internal state.

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