SH7136 datasheet(19/1160 Pages) RENESAS

19 / 1160 page

Rev. 2.00 Sep. 10, 2008 Page xix of xxvi

15.4.7 Clock Synchronous Communication Mode .......................................................... 632

15.5

SSU Interrupt Sources and DTC ........................................................................................ 638

15.6

Usage Notes ....................................................................................................................... 639

15.6.1 Module Standby Mode Setting ............................................................................. 639

15.6.2 Access to SSTDR and SSRDR Registers.............................................................. 639

15.6.3 Continuous Transmission/Reception in SSU Slave Mode .................................... 639

Section 16 I

2C Bus Interface 2 (I2C2) ................................................................641

16.1

Features.............................................................................................................................. 641

16.2

Input/Output Pins ...............................................................................................................644

16.3

Register Descriptions ......................................................................................................... 645

16.3.1 I

2C Bus Control Register 1 (ICCR1)..................................................................... 645

16.3.2 I

2C Bus Control Register 2 (ICCR2)..................................................................... 648

16.3.3 I

2C Bus Mode Register (ICMR)............................................................................ 650

16.3.4 I

2C Bus Interrupt Enable Register (ICIER) ........................................................... 652

16.3.5 I

2C Bus Status Register (ICSR)............................................................................. 654

16.3.6 I

2C Bus Slave Address Register (SAR)................................................................. 657

16.3.7 I

2C Bus Transmit Data Register (ICDRT)............................................................. 658

16.3.8 I

2C Bus Receive Data Register (ICDRR).............................................................. 658

16.3.9 I

2C Bus Shift Register (ICDRS)............................................................................ 658

16.3.10 NF2CYC Register (NF2CYC) .............................................................................. 659

16.4

Operation ........................................................................................................................... 660

16.4.1 I

2C Bus Format...................................................................................................... 660

16.4.2 Master Transmit Operation ................................................................................... 661

16.4.3 Master Receive Operation..................................................................................... 663

16.4.4 Slave Transmit Operation ..................................................................................... 666

16.4.5 Slave Receive Operation....................................................................................... 669

16.4.6 Clock Synchronous Serial Format ........................................................................ 670

16.4.7 Noise Filter ........................................................................................................... 674

16.4.8 Example of Use..................................................................................................... 675

16.5

2C2 Interrupt Sources........................................................................................................ 679

16.6

Operation Using the DTC .................................................................................................. 680

16.7

Bit Synchronous Circuit..................................................................................................... 681

16.8

Usage Note......................................................................................................................... 683

16.8.1 Module Standby Mode Setting ............................................................................. 683

16.8.2 Issuance of Stop Condition and Repeated Start Condition ................................... 683

16.8.3 Issuance of a Start Condition and Stop Condition in Sequence ............................ 683

16.8.4 Settings for Multi-Master Operation..................................................................... 684

16.8.5 Reading ICDRR in Master Receive Mode............................................................ 684

16.8.6 Supported Emulator .............................................................................................. 684

SH7136 Datasheet(PDF) 19 Page - Renesas Technology Corp

SH7136 Datasheet(HTML) 19 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL