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SH7136 Datasheet(PDF) 46 Page - Renesas Technology Corp |
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SH7136 Datasheet(HTML) 46 Page - Renesas Technology Corp |
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46 / 1160 page  Section 2 CPU Rev. 2.00 Sep. 10, 2008 Page 20 of 1130 REJ09B0402-0200 Bit Bit name Default Read/ Write Description 1 S Undefined R/W S Bit Used by the multiply and accumulate instruction. 0 T Undefined R/W T Bit Indicates true (1) or false (0) in the following instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT Indicates carry, borrow, overflow, or underflow in the following instructions: ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL • Global-base register (GBR) This register indicates a base address in GBR indirect addressing mode. The GBR indirect addressing mode is used for data transfer of the on-chip peripheral module registers and logic operations. • Vector-base register (VBR) This register indicates the base address of the exception handling vector table. |
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