SH7149 datasheet(108/1022 Pages) RENESAS

108 / 1022 page

Section 4 Clock Pulse Generator (CPG)

Rev. 3.00 May 17, 2007 Page 64 of 974

REJ09B0229-0300

Notes: *

Clock frequencies when the input clock frequency is assumed to be the shown value.

1. The PLL multiplication ratio is fixed at

×8. The division ratio can be selected from ×1,

×1/2, ×1/3, ×1/4, and ×1/8 for each clock by the setting in the frequency control register.

2. The output frequency of the PLL circuit is the product of the frequency of the input from

the crystal resonator or EXTAL pin and the multiplication ratio (

×8) of the PLL circuit.

3. The input to the divider is always the output from the PLL circuit.

4. The internal clock (I

φ) frequency is the product of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (

×8) of the PLL circuit, and the

division ratio of the divider. The resultant frequency must be a maximum of 80 MHz

(maximum operating frequency).

5. The bus clock (B

φ) frequency is the product of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (

×8) of the PLL circuit, and the

division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and

equal to or lower than the internal clock (I

φ) frequency.

6. The peripheral clock (P

φ) frequency is the product of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (

×8) of the PLL circuit, and the

division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and

equal to or lower than the bus clock (B

φ) frequency.

7. When using the MTU2S and MTU2, the MTU2S clock (MI

φ) frequency must be equal to

or lower than the internal clock (I

φ) frequency and equal to or higher than the MTU2

clock (MP

φ) frequency. The MTU2 clock (MPφ) frequency must be equal to or lower

than the MTU2S clock (MI

φ) frequency and the bus clock (Bφ) frequency, and equal to

or higher than the peripheral clock frequency (P

φ). The MTU2S clock (MIφ) frequency

and MTU2 clock (MP

φ) frequency are the product of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (

×8) of the PLL circuit, and the

division ratio of the divider.

8. The frequency of the CK pin is always be equal to the bus clock (B

φ) frequency.

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