SH7149 datasheet(112/1022 Pages) RENESAS

112 / 1022 page

Section 4 Clock Pulse Generator (CPG)

Rev. 3.00 May 17, 2007 Page 68 of 974

REJ09B0229-0300

4.4.2

Oscillation Stop Detection Control Register (OSCCR)

OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects

flag status output to an external pin. OSCCR can be accessed only in bytes.

Bit:

Initial value:

R/W:

7654321

00000000

RRRRRRR

R/W

-----

OSC

STOP

OSC

ERS

Bit

Bit Name

Initial

Value

R/W

Description

7 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

OSCSTOP 0

Oscillation Stop Detection Flag

[Setting conditions]

• When a stop in the clock input is detected during

normal operation

• When software standby mode is entered

[Clearing conditions]

• By a power-on reset input through the

RES pin

• When software standby mode is canceled



Reserved

This bit is always read as 0. The write value should

always be 0.

OSCERS

R/W

Oscillation Stop Detection Flag Output Select

Selects whether to output the oscillation stop

detection flag signal through the

WDTOVF pin.

0: Outputs only the WDT overflow signal through the

WDTOVF pin

1: Outputs the WDT overflow signal and the

oscillation stop detection flag signal through the

WDTOVF pin

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