SH7149 datasheet(111/1022 Pages) RENESAS

111 / 1022 page

Section 4 Clock Pulse Generator (CPG)

Rev. 3.00 May 17, 2007 Page 67 of 974

REJ09B0229-0300

Bit

Bit Name

Initial

Value

R/W

Description

8 to 6

PFC[2:0]

011

R/W

Peripheral Clock (P

φ) Frequency Division Ratio

Specify the division ratio of the peripheral clock (P

φ)

frequency with respect to the output frequency of PLL

circuit. If a prohibited value is specified, subsequent

operation is not guaranteed.

000:

×1

001:

×1/2

010:

×1/3

011:

×1/4

100:

×1/8

Other than above: Setting prohibited

5 to 3

MIFC[2:0]

011

R/W

MTU2S Clock (MI

φ) Frequency Division Ratio

Specify the division ratio of the MTU2S clock (MI

φ)

frequency with respect to the output frequency of PLL

circuit. If a prohibited value is specified, subsequent

operation is not guaranteed.

000:

×1

001:

×1/2

010:

×1/3

011:

×1/4

100:

×1/8

Other than above: Setting prohibited

2 to 0

MPFC[2:0] 011

R/W

MTU2 Clock (MP

φ) Frequency Division Ratio

Specify the division ratio of the MTU2 clock (MP

φ)

frequency with respect to the output frequency of PLL

circuit. If a prohibited value is specified, subsequent

operation is not guaranteed.

000:

×1

001:

×1/2

010:

×1/3

011:

×1/4

100:

×1/8

Other than above: Setting prohibited

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