SH7149 datasheet(119/1022 Pages) RENESAS

119 / 1022 page

Section 5 Exception Handling

Rev. 3.00 May 17, 2007 Page 75 of 974

REJ09B0229-0300

Section 5 Exception Handling

5.1

Overview

5.1.1

Types of Exception Handling and Priority

Exception handling is started by four sources: resets, address errors, interrupts and instructions and

have the priority, as shown in table 5.1. When several exceptions are detected at once, they are

processed according to the priority.

Table 5.1

Types of Exceptions and Priority

Exception

Exception Source

Priority

Reset

Power-on reset

High

Manual reset

Interrupt

User break (break before instruction execution)

Address error

CPU address error (instruction fetch)

Instruction

General illegal instructions (undefined code)

Illegal slot instruction (undefined code placed immediately after a

delayed branch instruction*

1 or instruction that changes the PC value*2)

Trap instruction (TRAPA instruction)

Address error

CPU address error (data access)

Interrupt

User break (break after instruction execution or operand break)

Address error

DTC address error (data access)

Interrupt

NMI

IRQ

On-chip peripheral modules

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and

BRAF.

2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,

TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.

SH7149 Datasheet(PDF) 119 Page - Renesas Technology Corp

SH7149 Datasheet(HTML) 119 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL