4502 datasheet(53/214 Pages) RENESAS

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4502 Group

HARDWARE

Rev.2.01

Feb 02, 2005

REJ09B0193-0201

RAM BACK-UP MODE

The 4502 Group has the RAM back-up mode.

When the POF or POF2 instruction is executed continuously after

the EPOF instruction, system enters the RAM back-up state.

The POF or POF2 instruction is equal to the NOP instruction when

the EPOF instruction is not executed before the POF or POF2 in-

struction.

As oscillation stops retaining RAM, the function of reset circuit and

states at RAM back-up mode, current dissipation can be reduced

without losing the contents of RAM.

In the RAM back-up mode by the POF instruction, system enters

the RAM back-up mode and the voltage drop detection cicuit keeps

operating.

In the RAM back-up mode by the POF2 instruction, all internal

periperal functions stop.

Table 15 shows the function and states retained at RAM back-up.

Figure 39 shows the state transition.

(1) Identification of the start condition

Warm start (return from the RAM back-up state) or cold start (re-

turn from the normal reset state) can be identified by examining the

state of the power down flag (P) with the SNZP instruction.

(2) Warm start condition

When the external wakeup signal is input after the system enters

the RAM back-up state by executing the EPOF instruction and

POF or POF2 instruction continuously, the CPU starts executing

the program from address 0 in page 0. In this case, the P flag is

“1.”

(3) Cold start condition

The CPU starts executing the program from address 0 in page 0

when;

• reset pulse is input to RESET pin, or

• reset by watchdog timer is performed, or

• voltage drop detection circuit is detected by the voltage drop

In this case, the P flag is “0.”

Table 15 Functions and states retained at RAM back-up

Function

Program counter (PC), registers A, B,

carry flag (CY), stack pointer (SP) (Note 2)

Contents of RAM

Port level

Selected oscillation circuit

Timer control register W1

Timer control registers W2, W6

Clock control register MR

Interrupt control registers V1, V2

Interrupt control register I1

Timer 1 function

Timer 2 function

A/D conversion function

Voltage drop detection circuit

A/D control register Q1

Pull-up control registers PU0 to PU2

Key-on wakeup control registers K0 to K2

External 0 interrupt request flag (EXF0)

Timer 1 interrupt request flag (T1F)

Timer 2 interrupt request flag (T2F)

Watchdog timer flags (WDF1)

Watchdog timer enable flag (WEF)

16-bit timer (WDT)

A/D conversion completion flag (ADF)

Interrupt enable flag (INTE)

POF2

(Note 6)

(Note 3)

✕ (Note 4)

Notes 1: “O” represents that the function can be retained, and “✕” repre-

sents that the function is initialized.

Registers and flags other than the above are undefined at RAM

back-up, and set an initial value after returning.

2: The stack pointer (SP) points the level of the stack register and is

initialized to “7” at RAM back-up.

3: The state of the timer is undefined.

4: Initialize the watchdog timer flag WDF1 with the WRST instruction,

and then execute the POF or POF2 instruction.

5: This function is operating in the RAM back-up mode. When the

voltage drop is detected, system reset occurs.

6: As for the D2/C pin, the output latch of port C is set to “1” at the

RAM back-up. However, the output latch of port D2 is retained.

As for the other ports, their output levels are retained at the RAM

back-up.

RAM back-up

POF

(Note 6)

(Note 3)

O (Note 5)

(Note 3)

✕ (Note 4)

FUNCTION BLOCK OPERATIONS

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