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4502 Datasheet(PDF) 18 Page - Renesas Technology Corp

Part # 4502
Description  4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
PDF  214 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4502 Datasheet(HTML) 18 Page - Renesas Technology Corp

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1-6
Rev.2.01
Feb 02, 2005
4502 Group
HARDWARE
REJ09B0193-0201
DEFINITION OF CLOCK AND CYCLE
q Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• External ceramic resonator
• External RC oscillation
• Clock (f(XIN)) by the external clock
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator.]
q System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bits 2 and 3 of the clock con-
trol register MR.
Register MR
System clock
(Note 1)
f(XIN) or f(RING)
f(XIN)/2 or f(RING)/2
f(XIN)/4 or f(RING)/4
f(XIN)/8 or f(RING)/8
Table Selection of system clock
Notes 1: The on-chip oscillator clock is f(RING), the clock by the
ceramic resonator, RC oscillation or external clock is
f(XIN).
2: The default mode is selected after system is released
from reset and is returned from RAM back-up.
MR2
0
1
0
1
MR3
0
0
1
1
Operation mode
High-speed mode
Middle-speed mode
Low-speed mode
Default mode
q Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
q Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
PORT FUNCTION
Port
Port D
Port P0
Port P1
Port P2
Port P3
I/O
unit
1
4
4
2
2
Control
instructions
SD, RD
SZD, CLD
SCP, RCP
SNZCP
IAK, OKA
OP0A
IAP0
OP1A
IAP1
OP2A
IAP2
OP3A
IAP3
Control
registers
PU2, K2
PU0, K0
PU1, K1
W6, I1
PU2, K2
Q1
Q1
Output structure
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
Input
Output
I/O
(6)
I/O
(4)
I/O
(4)
I/O
(2)
I/O
(2)
Remark
Pin
D0, D1, D4, D5
D2/C
D3/K
P00–P03
P10, P11
P12/CNTR,
P13/INT
P20/AIN0
P21/AIN1
P30/AIN2
P31/AIN3
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
PIN DESCRIPTION



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